화학공학과

Research Description

overview

Our research mainly focuses on etching and deposition of various thin films for the fabrication of microelectronics and microelectromechanical systems (MEMS) devices, nanotechnology,

surface modification of materials, and so on.

Plasma processing and electrochemical methods are used to elucidate fundamental phenomena and mechanisms during etching and deposition of thin films.

The following describes briefly the current research interest.

Atomic Scale Plasma Etching for the Fabrication of Nano-structures As device dimensions keep shrinking below 100 nm, control of film thickness down to atomic level is increasingly required for the fabrication of extremely thin layers used in many devices.

We have developed "Atomic Scale Etching (ASE)" of poly-Si, which can give etching with atomic scale accuracy, in inductively coupled Ar and He plasmas. The process window for the realization of ASE could be obtained by varying ion energy.

Within the process window for ASE, etch rates were found to be self-limited with respect to ion energy, confirming that ASE of poly-Si was obtained at this condition.

The use of a Faraday cage system to measure the angular dependence of etch rates revealed etch mechanisms within and outside the process windows for the realization of ASE.

Mechanism and Chemistry of Deep Si Etching Plasma etching of high aspect ratio features of Si is a key process in the fabrication of Si-based MEMS devices. The Bosch process, which is known as a gas-chopping etching or time-multiplexed etching, is currently in widespread use for deep Si etching. It is a cyclic process, consisting of sequentially alternating etch and deposition steps. To date, most studies on deep Si etching have been confined to the observation of etch characteristics of blank substrate or final etch profiles obtained by changing the process variables. However, these studied do not permit an understanding of the mechanism of this process and an identification of the optimal process conditions required to yield high aspect ratio and anisotropy. During deep Si etching, various phenomena take place simul taneously such as ion-induced etching, chemical etching of the sidewall by reactive radicals, polymer deposition due to radicals, the redeposition of particles emitted from the bottom, and so on.

For better understanding of deep Si etching mechanism, we used a Faraday cage, a specially designed substrate, and sample holders. This allows one to measure individual rates of lateral and vertical etching and the angular dependence of etch rates. Based on these measurements, optimum conditions for bias voltage and source power for each step of the deep Si etching could be proposed, obtaining an anisotropic etch profiles. We have also demonstrated that the use of a Faraday cage combined with a high bias voltage in the etching step produced an etch profile combined with a high bias voltage in the etching step produced an etch profile Currently, SF and C₄F are mainly used in the etching and deposition steps of the deep Si etching, respectively. However, CF is perfluoro carbon (PFC), which is considered to be problematic from an environmental point of view because of its long atmospheric lifetime, high global warming potential, and strong infrared absorption. In order to reduce PFC emission during deep Si etching, we developed alternative chemistries to PFC for deep Si etching.

Based on understanding of the characteristics of fluorocarbon films produced in PFC and non-PFC plasmas, highly anisotropic Si etching can be successfully achieved in both PFC and non-PFC plasmas.

Electro and Electroless Deposition of capping/barrier Layers for Cu Interconnection The use of copper for wiring in the fabrication of microelectronic devices and MEMS has some advantages over aluminum wiring such as low electrical resistance, higher allowed current density, good reliability, and higher electromigration resistance. Major drawbacks for copper metallization, however, are its oxidation and diffusion into oxide layers, which degrade the performance of the devices.

To prevent copper from oxidation and diffusion, barrier/capping layers have been introduced.

Among them, composite films in the form of iron group metal-refractory metal-P(or B) have been found very promising.

We have developed baths for electrodeposition of CoWP and NiMoP as capping/barrier layers for Cu interconnection. Electrochemical studies (using voltammetry and chronoamperometry) were carried out to find out a rate-determining step and nucleation mechanism for the deposition of CoWP and NiMoP films. The investigation of the effects of process variables (such as electrolyte concentration, PH, temperature, etc.) on thickness, composition, and microstructure of the films could explain chemical and physical behaviors of the films.

CoWP and NiMoP films were also deposited by an electroless plating method using alkali metal-free electrolytes. Due to unique characteristic of electroless plating, electrolessly deposited CoWP and NiMop films showed interesting results.

CoWP films can also be useful for other technological applications since Co-based alloy have good magnetic, physical, and mechanical properties. We investigated coating properties of CoWP films and find out that hardness and corrosion resistance of the CoWP films could be greatly improved, compared to Cr coating.

지도교수 소개

• 교수명 : 김창구
• 직위 : 아주대학교 화학공학과 교수
• 연구실 위치 : 팔달관 501호
• 연락처 (교내) : 031-219-2389
• FAX : 031-219-1612
• E-mail : changkoo@ajou.ac.kr

학력(기간)

• 1988.3~1992.2 : 서울대학교 화학공학과(학사)
• 1992.3~1995.8 : 서울대학교 화학공학과(석사)
• 1996.8~2000.12 : Department of Chemical Engineering University of Houston(Ph.D)

경력(기간)

• 2001.1~2002.2 : Senior process engineer. Novellus (San Jose ,CA)
• 2002.3~2006.2 : 아주대학교 조교수
• 2006.3~2011.2 : 아주대학교 부교수
• 2011.3~현재 : 아주대학교 교수